DocumentCode
2706291
Title
A high random-access-data-rate 4 Mb DRAM with pipeline operation
Author
Furuyama, Tohru ; Kushiyama, Natsuki ; Watanabe, Yohji ; Ohsawa, Takashi ; Muraoka, Kazuyoshi ; Nagahama, Yousei
fYear
1990
fDate
7-9 June 1990
Firstpage
9
Lastpage
10
Abstract
A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e. a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAD access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family
Keywords
DRAM chips; VLSI; integrated circuit technology; integrated memory circuits; pipeline processing; 10 MHz; 100 ns; 20 ns; 4 Mbit; DRAM; VLSI; circuit technology; cycle time; data rate; fast virtual RAD access time; high random-access-data-rate; pipeline DRAM; pipeline operation; pipeline scheme; read operation; standard DRAM family;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location
Honolulu, Hawaii, USA
Type
conf
DOI
10.1109/VLSIC.1990.111072
Filename
5727506
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