DocumentCode :
2706328
Title :
Parasitic capacitance effects of the multilevel interconnects in DRAM circuits
Author :
Yuan, J.S. ; Liou, J.J.
Author_Institution :
Univ. of Central Florida, Orlando, FL, USA
fYear :
1990
fDate :
12-13 Jun 1990
Firstpage :
410
Lastpage :
412
Abstract :
The parasitic capacitance effects of the multilevel interconnects in DRAM circuits have been studied. Signal crosstalk such as intra- and inter-bit-line-to-bit-line coupling, bit-line-to-work-line coupling, and substrate noise coupling resulting from various parasitic capacitances between interconnects are presented. The intra-bit-line capacitance coupling and bit-line capacitance imbalance effects reduce the initial voltage difference between bit lines and degrade the sense amplifier sensing speed. The inter-bit-line capacitive coupling and bit-line-to-word-line signal crosstalk introduce significant array noise in multimegabit DRAMs. The depletion capacitance between n+ diffusion and p substrate offers a channel of the substrate interference noise during sense amplifier amplification
Keywords :
DRAM chips; VLSI; capacitance; crosstalk; metallisation; DRAM circuits; array noise; depletion capacitance; inter-bit-line capacitive coupling; memory IC; multilevel interconnects; multimegabit DRAMs; n+ diffusion; p substrate; parasitic capacitance effects; signal crosstalk; substrate noise coupling; Circuit noise; Coupling circuits; Crosstalk; Equations; Integrated circuit interconnections; Mutual coupling; Parasitic capacitance; Pulse amplifiers; Random access memory; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE
Conference_Location :
Santa Clara, CA
Type :
conf
DOI :
10.1109/VMIC.1990.127915
Filename :
127915
Link To Document :
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