• DocumentCode
    2706342
  • Title

    A divided/shared bitline sensing scheme for 64 Mb DRAM core

  • Author

    Hidaka, Hideto ; Matsuda, Yoshio ; Fujishima, Kazuyasu

  • fYear
    1990
  • fDate
    7-9 June 1990
  • Firstpage
    15
  • Lastpage
    16
  • Abstract
    New high-density DRAM core designs based on a new divided bitline sensing principle are proposed and their performance is estimated. These designs can achieve a high-density memory cell array and can also overcome problems of the scaled memory array. These designs are promising candidates for 64-Mb DRAM and beyond
  • Keywords
    DRAM chips; VLSI; integrated circuit technology; integrated memory circuits; 64 Mb DRAM core; 64 Mbit; ULSI; divided bitline sensing; divided/shared bitline sensing scheme; high-density DRAM core designs; high-density memory cell array; performance; scaled memory array;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
  • Conference_Location
    Honolulu, Hawaii, USA
  • Type

    conf

  • DOI
    10.1109/VLSIC.1990.111075
  • Filename
    5727509
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2706342