DocumentCode :
2706371
Title :
A 1.5 V circuit technology for 64 Mb DRAMs
Author :
Nakagome, Y. ; Kawamoto, Y. ; Tanaka, H. ; Takeuchi, K. ; Kume, E. ; Watanabe, Y. ; Kaga, T. ; Murai, F. ; Izawa, R. ; Hisamoto, D. ; Kisu, T. ; Nishida, T. ; Takeda, E. ; Itoh, K.
fYear :
1990
fDate :
7-9 June 1990
Firstpage :
17
Lastpage :
18
Abstract :
A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future
Keywords :
DRAM chips; VLSI; integrated circuit technology; integrated memory circuits; technological forecasting; 1.5 V; 1.5 V circuit technology; 44 mW; 50 ns; 64 Mb DRAMs; 64 Mbit; RAS access time; ULSI; low-voltage battery-operated DRAM; low-voltage circuit technology; power dissipation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
Type :
conf
DOI :
10.1109/VLSIC.1990.111076
Filename :
5727510
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2706371
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