Title :
A 7 ns 1 Mb BiCMOS ECL SRAM with program-free redundancy
Author :
Ohba, A. ; Ohbayashi, S. ; Shiomi, T. ; Takano, S. ; Anami, K. ; Honda, H. ; Ishigaki, Y. ; Hatanaka, M. ; Nagao, S. ; Kayano, S.
Abstract :
A 7-ns, 1 M×1/256 K×4 BiCMOS ECL (emitter coupled logic) SRAM with program-free redundancy is described. To obtain the fast address access time and low power consumption, an improved ECL buffer and two-stage sensing scheme were adopted. The SRAM was fabricated with a 0.8-μm double-poly-Si double-metal BiCMOS technology. The RAM has an ECL 10 K interface and operates at a supply voltage of -5.2 V. An access time of 7 ns has been obtained. Active 680 mW for ×4 mode. The cell size is 5.4 μm×7.2 μm (38.88 μm2); the die size is 5.46 mm×16.16 mm (88.24 mm2)
Keywords :
BIMOS integrated circuits; SRAM chips; VLSI; emitter-coupled logic; integrated circuit technology; integrated memory circuits; -5.2 V; 0.8 micron; 1 Mbit; 16.16 mm; 5.4 micron; 5.46 mm; 50 MHz; 600 mW; 680 mW; 7 ns; 7.2 micron; BiCMOS; ECL 10 K interface; ECL I/O; ECL buffer; SRAM; ULSI; access time; cell size; die size; double-poly-Si double-metal BiCMOS technology; emitter coupled logic; organisation 1 M×1; organisation 256 K×4; program-free redundancy; supply voltage; two-stage sensing scheme;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111085
