Title :
An experimental 5 ns BiCMOS SRAM with a high-speed architecture
Author :
Fung, K. ; Suzuki, T. ; Terazawa, J. ; Khayami, A. ; Martindell, S. ; Blanton, C. ; Tran, H. ; Eklund, R. ; Madan, S. ; Holloway, T. ; Rodder, M. ; Graham, J. ; Chapman, R. ; Haken, R. ; Scott, D.
Abstract :
A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by today´s systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-μm BiCMOS technology. The chip is organized as 128 K-words×8-b wide using a 4T2R memory cell of 28 μm2
Keywords :
BIMOS integrated circuits; SRAM chips; VLSI; integrated circuit technology; integrated memory circuits; 0.6 micron; 1 Mbit; 128 Kbyte; 4T2R memory cell; 5 ns; 8 bit; BiCMOS SRAM; BiCMOS technology; ULSI; access time; architectural innovation; circuit techniques; current sense amplifier; high-speed architecture; input buffer/level translator; organisation 128 K×8;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111086
