• DocumentCode
    2706699
  • Title

    A self-learning neural network chip with 125 neurons and 10 K self-organization synapses

  • Author

    Arima, Yutaka ; Mashiko, Koichiro ; Okada, Keisuke ; Yamada, Tsuyoshi ; Maeda, Atushi ; Kondoh, Harufusa ; Kayano, Shinpei

  • fYear
    1990
  • fDate
    7-9 June 1990
  • Firstpage
    63
  • Lastpage
    64
  • Abstract
    The authors propose a neural network chip that can organize the connection weight of each synapse with 125 neurons so that it can learn on chip. The chip employs the mixed design architecture of digital and analog circuits in a 1.0-μm CMOS technology. The chip operates more than 1000 times faster than conventional computers
  • Keywords
    CMOS integrated circuits; application specific integrated circuits; learning systems; neural nets; 1.0 micron; CMOS technology; connection weight; mixed design architecture; self-learning neural network chip; self-organization synapses;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
  • Conference_Location
    Honolulu, Hawaii, USA
  • Type

    conf

  • DOI
    10.1109/VLSIC.1990.111096
  • Filename
    5727529
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2706699