Title :
A self-learning neural network chip with 125 neurons and 10 K self-organization synapses
Author :
Arima, Yutaka ; Mashiko, Koichiro ; Okada, Keisuke ; Yamada, Tsuyoshi ; Maeda, Atushi ; Kondoh, Harufusa ; Kayano, Shinpei
Abstract :
The authors propose a neural network chip that can organize the connection weight of each synapse with 125 neurons so that it can learn on chip. The chip employs the mixed design architecture of digital and analog circuits in a 1.0-μm CMOS technology. The chip operates more than 1000 times faster than conventional computers
Keywords :
CMOS integrated circuits; application specific integrated circuits; learning systems; neural nets; 1.0 micron; CMOS technology; connection weight; mixed design architecture; self-learning neural network chip; self-organization synapses;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111096
