• DocumentCode
    2706740
  • Title

    A fully operational 1-kbit variable threshold Josephson RAM

  • Author

    Kurosawa, I. ; Nakagawa, H. ; Aoyagi, M. ; Kosaka, S. ; Takada, S.

  • fYear
    1990
  • fDate
    7-9 June 1990
  • Firstpage
    67
  • Lastpage
    68
  • Abstract
    A 1-kb Josephson RAM chip in which all bits are operational has been demonstrated. The chip employs a new Josephson memory cell called the variable threshold memory cell. The cell has a simple structure and a wide operating margin. A directly coupled logic circuit has been introduced to drive a memory cell array instead of a superconducting loop circuit as used in previous Josephson RAM chips The directly coupled logic circuit using 4JL (four Josephson-junction logic) gates is superior because it applies a well-defined driving current to the memory cells. As a result, a fully operational Josephson RAM is realized. Experimental results on this RAM are presented
  • Keywords
    Josephson effect; cellular arrays; random-access storage; superconducting memory circuits; 1 kbit; 4JL gates; Josephson memory cell; directly coupled logic circuit; driving current; memory cell array; operating margin; variable threshold Josephson RAM; variable threshold memory cell;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
  • Conference_Location
    Honolulu, Hawaii, USA
  • Type

    conf

  • DOI
    10.1109/VLSIC.1990.111098
  • Filename
    5727531