Title :
A 7.6 K-gate Josephson macrocell array
Author :
Kotani, S. ; Inoue, A. ; Hasuo, S.
Abstract :
The design and technology for a high-speed Josephson macrocell array are described. A macrocell array including 7.6 k gates was fabricated using a 1.5-μm Nb Josephson process. The chip dimensions are 5×5 mm, and its power consumption is 23 mW. An average gate delay in full adder of 5.3 ps has been achieved using the macrocell
Keywords :
Josephson effect; adders; cellular arrays; niobium; superconducting logic circuits; 1.5 micron; 23 mW; Josephson macrocell array; Nb; average gate delay; chip dimensions; full adder; power consumption;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111099
