A new soft-error phenomenon in ULSI SRAMs-inverted dependence of soft-error rate on cycle time

The inverted dependence of the soft-error rate (SER) on the cycle time in static RAMs with high resistive load cells is described. The inverted dependence is observed in the SRAM with a PMOS bit-line load. At a cycle time of 100 ns, the SER is reduced by 1.5 orders of magnitude, compared with that of the SRAM with NMOS bit-line load. The mechanism is explained with reference to the time constant of the potential drop of the high storage node in the selected cell. It is concluded that the PMOS bit-line load is an effective method for improving the SER when the subthreshold current through the driver transistor is reduced. This technique shows potential for ULSI SRAMs beyond 4 Mb