Title :
Wordline coupling noise reduction techniques for scaled DRAMs
Author :
Min, Dong-Sun ; Seo, Dong-Il ; You, Jehwan ; Cho, Sooin ; Chin, Daeje ; Park, Y.E.
Abstract :
The wordline architecture of the twisted word line (TWL) scheme and a wordline latch circuit for suppressing wordline coupling noise have been proposed and demonstrated. Using this approach, wordline coupling noise is reduced by 70% compared to the conventional wordline structure. This technique was found to be effective for suppressing wordline coupling noise with minimum layout penalty in scaled high-density DRAMs
Keywords :
DRAM chips; memory architecture; coupling noise reduction techniques; high-density DRAMs; minimum layout penalty; scaled DRAMs; twisted word line; wordline architecture; wordline latch circuit;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111105
