Environment and methodology for accurate noise simulation of VLSI circuits

An integrated simulation environment which accurately models the noise behavior of VLSI circuits in a package with reasonable simulation time has been developed. These models are generated by automatic tools developed for this purpose. When used in a methodical approach to noise analysis, the tools speed up the simulation process and make it possible to reliably predict the behavior of a VLSI circuit in a package before it is fabricated. Theoretical package-pin models have been correlated with scattering parameter measurements, SPICE simulations, electrical-parameter simulation, and bench measurements. Die parasitics are automatically extracted to produce a compact die model. Models for the package-pins, the die capacitance, the active circuits, and the output loads are combined to simulate the noise behavior of a circuit