Bitwise Competition Logic for compact digital comparator

Author

Kim, Joo-Young ; Yoo, Hoi-Jun

Author_Institution

Korea Adv. Inst. of Sci. & Technol., Daejeon

fYear

2007

fDate

12-14 Nov. 2007

Firstpage

59

Lastpage

62

Abstract

In this paper, we present a bitwise competition logic (BCL) for the high performance and area efficient digital comparator. It compares two integer numbers using the location of the first 1 from the MSB, without arithmetic computations. The detail circuits to implement BCL, pre-encoder and selection logics are explained. The implemented BCL comparator shows 16%, 38% and 30% improved result in propagation delay, transistor count, and physical area compared to the other types of comparators. Measurement waveforms of fabricated BCL comparator verify its feasibility and functionality.

Keywords

comparators (circuits); digital circuits; logic circuits; transistors; arithmetic computations; bitwise competition logic; compact digital comparator; pre-encoder; propagation delay; transistor count; Adders; CMOS logic circuits; CMOS process; Digital arithmetic; Digital systems; Equations; Logic circuits; Propagation delay; Semiconductor device measurement; Solid state circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian

Conference_Location

Jeju

Print_ISBN

978-1-4244-1359-1

Electronic_ISBN

978-1-4244-1360-7

Type

conf

DOI

10.1109/ASSCC.2007.4425682

Filename

4425682