A 2.5V, 5mW UMTS and GSM dual mode decimation filter for sigma delta ADC

This paper describes a decimation processor for a dual-mode sigma-delta ADC for GSM and UMTS mobile standards. Partly contradictory requirements like high dynamic range and low bandwidth for GSM and vice versa for UMTS need decimation factors of M=144 (GSM) and M=8 (UMTS). A multi-rate filter architecture, which allows best hardware re-use for both mobile standards, is selected. Since the ADC is to be integrated into the power management component of the mobile terminal utilizing a 0.35 mum CMOS technology, special attention has been given to silicon area and power consumption of the component, while maintaining a standard design flow for the implementation. The processor covers 1.13 mm² of silicon and consumes 4.72 mW in GSM and 5.54 mW in UMTS mode, both at V_dd=2.5 V.