A 36 ns 1 Mbit CMOS EPROM with new data sensing technique

A 36-ns, 1-Mb EPROM using a unique pseudodifferential sensing technique for high speed and a new noise immunity technique has been developed. In order to achieve both high speed and small die size, a newly developed pseudodifferential sensing technique with single-ended bit lines (one transistor/cell) and only two reference bit lines has been implemented, instead of a conventional fully differential sensing technique which has the disadvantage of large die size. A new data transfer circuit whose data transfer speed is controlled by an address transition detection pulse is utilized to obtain high noise immunity against power line noise caused by charging or discharging an output capacitance. Using 0.9-μm lithography, a cell size of 3.1 μm×2.9 μm has been achieved, resulting in a small die size of 6.67 mm×6.56 mm. The chip is fabricated by an n-well CMOS double poly-Si process with polycide technology and a single metal