Title :
A novel automatic erase technique using an internal voltage generator for 1 Mbit flash EEPROM
Author :
Shohji, Kazuyoshi ; Wada, Takeshi ; Seki, Kohichi ; Mutoh, Tadashi ; Noda, Takaaki ; Kubota, Yasuroh ; Hagiwara, Takaaki ; Shimohigashi, Katsuhiro
Abstract :
An on-chip automatic erase technique using an internal voltage generator has been developed and has proved to operate well in 1-Mb-flash EEPROM. This technology permits accurate control of erasure and guarantees the performance after erasure of the true single-transistor-per-cell type of flash EEPROM. Device implementation is described
Keywords :
CMOS integrated circuits; EPROM; integrated memory circuits; 1 Mbit; automatic erase technique; double well CMOS; flash EEPROM; internal voltage generator; onchip erase scheme; single-transistor-per-cell type;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111114
