DocumentCode
2707118
Title
A 0.67μW/MHz, 5ps jitter, 4 locking cycles, 65nm ADDLL
Author
Wang, Jinn-Shyan ; Cheng, Chun-Yuan ; Liu, Yu-Chia ; Wang, Yi-Ming
Author_Institution
Nat. Chung-Cheng Univ., Chia-Yi
fYear
2007
fDate
12-14 Nov. 2007
Firstpage
300
Lastpage
303
Abstract
This paper presents the design of a 1.0 V 150-550 MHz 65 nm ADDLL using a novel coarse-fine architecture and differential circuit techniques. When running at 550 MHz, this nanometer ADDLL achieves a peak-to-peak jitter of only 5 ps with the shortest 4 locking cycles, while consumes only 0.67 muW/MHz, about 72% reduction compared to the existing most power efficient ADDLL.
Keywords
delay lock loops; differentiating circuits; jitter; coarse-fine architecture; delay locked loops; differential circuit; frequency 150 MHz to 550 MHz; jitter; locking cycles; nanometer ADDLL; size 65 nm; time 5 ps; voltage 1.0 V; Capacitors; Clocks; Delay lines; Frequency; Jitter; Latches; Pulse measurements; Shift registers; Solid state circuit design; Solid state circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location
Jeju
Print_ISBN
978-1-4244-1359-1
Electronic_ISBN
978-1-4244-1360-7
Type
conf
DOI
10.1109/ASSCC.2007.4425690
Filename
4425690
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