Title :
Pipelined, time-sharing access technique for a highly integrated multi-port memory
Author :
Matsumura, Tsuneo ; Endo, Ken-ichi ; Yamada, Junzo
Abstract :
A pipelined, time-sharing access (PTA) technique that enables a two-port memory cell to operate as a four-port memory cell is proposed. The effectiveness of this technique has been demonstrated by fabricating a 64-kb four-port (read/write) memory with 60-MHz operation under a 3-V supply voltage
Keywords :
CMOS integrated circuits; integrated memory circuits; pipeline processing; 3 V; 60 MHz; 64 kbit; four-port memory cell; integrated multi-port memory; n-well CMOS; pipelined technique; time-sharing access technique; two-port memory cell;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111118
