Title :
Very-Low-Voltage testing of amorphous silicon TFT circuits
Author :
Shen, Shiue-Tsung ; Liu, Wei-Hsiao ; Li, James Chien-Mo ; Cheng, I-Chun
Author_Institution :
Lab. of Dependable Syst., Grad. Inst. of Electron. Eng., Taiwan
Abstract :
This poster presents very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin-film (a-Si TFT) transistor technology as an economic alternative to burn-in. A total number of 140 CUT implemented in 8¿m a-Si TFT technology are tested at nominal voltage and very-low-voltage. The results indicate that VLV testing is effective in screening out unreliable a-Si TFT circuits.
Keywords :
MOS integrated circuits; digital circuits; integrated circuit testing; low-power electronics; silicon; thin film transistors; amorphous silicon thin-film transistor technology; digital NMOS circuits; size 8 mum; very-low-voltage testing; Amorphous silicon; CMOS technology; Circuit testing; Delay effects; Electronic equipment testing; Stress; System testing; Thin film transistors; Time measurement; Voltage;
Conference_Titel :
Test Conference, 2009. ITC 2009. International
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4868-5
Electronic_ISBN :
978-1-4244-4867-8
DOI :
10.1109/TEST.2009.5355808
