DocumentCode
2707198
Title
Architecture and design of a second-level cache chip with copy-back and 160 MB/s burst-transfer features
Author
Uchiyama, Kenji ; Aoki, Hidetaka ; Nishii, O. ; Hatano, S. ; Nagashima, O. ; Ooishi, K. ; Kitano, J.
fYear
1990
fDate
7-9 June 1990
Firstpage
115
Lastpage
116
Abstract
The authors describe the architecture and design of a second-level cache chip which supports high-speed (160-Mb/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. This chip includes a 32-kB data memory as well as a 42-kb tag memory and 21.7 K-gate logic, and it supports a 50-MHz CPU. Performance and design results are presented
Keywords
buffer storage; integrated memory circuits; 160 MByte/s; 32 kB; 42 kbit; 50 MHz; burst-transfer features; copy-back; data memory; multilevel caches; second-level cache chip; tag memory;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location
Honolulu, Hawaii, USA
Type
conf
DOI
10.1109/VLSIC.1990.111122
Filename
5727555
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