VLSI implementation of modulo-arithmetic units using 2-D cellular automata

The VLSI implementation of a mod-127 multiplier using 2-D cellular automata (CA) is presented. The principle of operation of the multiplier is based on two identical 12×12 null-bounded CA each having semi-group order 126. In practice, implementation utilizes the data compression capabilities of CA to reduce the area required by these arrays by about 90%. This is achieved by using triangular CA, each comprising 15 cells having appropriately chosen inertial boundary conditions. Encoding and decoding is performed on-chip and the complexity of this task is significantly reduced by observing only critical cells when ascertaining the state of a cellular automation. The main objective of this work was to determine performance and area requirements for this simpler tasks so predictions can then be made for more substantial units