Title :
A 10 ns 54×54-bit parallel structured full array multiplier with 0.5 μm CMOS technology
Author :
Mori, J. ; Nagamatsu, M. ; Hirano, M. ; Tanaka, S. ; Noda, M. ; Toyoshima, Y. ; Hashimoto, K. ; Hayashida, H. ; Maeguchi, K.
Abstract :
A 54-b×54-b multiplier fabricated in double metal 0.5-μm CMOS technology is described. A 10-ns multiplication time has been achieved by employing a 4-2 compressor, a carry select adder, and a carry lookahead adder. The 54-b×54-b full array is adopted to complete the multiplication within one latency. This multiplier is intended for double-precision floating-point data processing based on IEEE standards up to a clock range of 100 MHz. The multiplier has integrated 81600 transistors in an active area of 3.62 mm×3.45 mm
Keywords :
CMOS integrated circuits; carry logic; logic arrays; multiplying circuits; 0.5 micron; 10 ns; 100 MHz; CMOS technology; IEEE standards; carry lookahead adder; carry select adder; digital arithmetic; double metal technology; double-precision floating-point data processing; parallel structured full array multiplier;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111127
