Title :
4.8GHz CMOS frequency multiplier with subharmonic pulse-injection locking
Author :
Takano, Kyoya ; Motoyoshi, Mizuki ; Fujishima, Minoru
Author_Institution :
Tokyo Univ., Tokyo
Abstract :
To realize low-power wireless transceivers, it is required to improve the performance of a frequency synthesizer, which is typically used as a frequency multiplier and is composed of a phase-locked loop (PLL). However a general PLL consumes much power and occupies a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFYM), in which spurious signals are suppressed by using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18 mum 1P5M CMOS process. The core size was 10.8 mum x 10 S mum. The power consumption of the ILO is 9.6 muW at 250 MHz, and 1.47 mW at 4.8 GHz. The phase noise is -108 dBc/Hz at 1 MHz offset. For a ten-times frequency multiplier, output phase noise is 10 JB larger than the input phase noise below 10 kHz offset, which is the theoretical limit.
Keywords :
CMOS analogue integrated circuits; circuit noise; frequency multipliers; frequency synthesizers; injection locked oscillators; phase locked loops; phase noise; 1P5M CMOS process; CMOS frequency multiplier; PLL; frequency 250 MHz; frequency 4.8 GHz; frequency synthesizer; injection-locked oscillator; phase noise; phase-locked loop; power 1.47 mW; power 9.6 muW; power consumption; pulse input signal; pulse-injection-locked frequency multiplier; size 0.18 mum; size 10.5 mum; size 10.8 mum; spurious signals; subharmonic pulse-injection locking; Energy consumption; Filters; Frequency conversion; Frequency synthesizers; Injection-locked oscillators; MOS devices; Phase locked loops; Phase noise; Transceivers; Wireless sensor networks;
Conference_Titel :
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4244-1359-1
Electronic_ISBN :
978-1-4244-1360-7
DOI :
10.1109/ASSCC.2007.4425699