A 130 nm CMOS 6-bit full nyquist 3GS/s DAC

This paper presents a 6-bit high-speed, low-power digital-to-analog converter (DAC). It is based on a current steering binary weighted architecture and achieves 10-bit accuracy without calibration. Due to the absence of a thermometer decoder, the operating speed can be up to 4.5 GS/s. The DAC occupies 0.4 mm times 0.5 mm in a standard 130 nm CMOS technology. A spurious-free dynamic range (SFDR) of more than 36 dB has been measured over the complete Nyquist interval at sampling frequencies up to 3 GS/s. The power consumption at a 3 GHz clock frequency for a near-Nyquist sinusoidal output signal equals 29 mW.