Title :
A 14-bit 100-MS/s digitally calibrated binary-weighted current-steering CMOS DAC without calibration ADC
Author :
Ikeda, Yusuke ; Frey, Matthias ; Matsuzawa, Akira
Author_Institution :
Tokyo Inst. of Technol., Tokyo
Abstract :
A 14-bit digitally calibrated digital-to-analog converter (DAC) is presented. This DAC uses a simple current comparator for the current measurement during calibration instead of a high-resolution ADC. Therefore, compared to a calibration scheme utilizing a high-resolution ADC, a faster calibration cycle is possible with smaller additional circuits. To reduce the additional area for calibration and error compensation, the lowest 8-bit DAC is used for both error correction and for normal operation; the additional DACs required for calibration are only of 3-bit and of 7-bit resolution. Nevertheless, a large calibration range is attained. Full 14-bit resolution is achieved on a small chip-area (0.72 mm2). The measurement results show that the spurious free dynamic range is 83.4 (46.6) dBc for signals of 6 kHz (30 MHz) at an update rate of 100 MS/s.
Keywords :
CMOS digital integrated circuits; calibration; current comparators; digital-analogue conversion; error compensation; error correction; CMOS integrated circuit; binary weighted DAC; current comparator; current measurement; current steering; digital calibration; digital-analog converter; error compensation; error correction; word length 14 bit; Calibration; Circuits; Costs; Current measurement; Delta-sigma modulation; Digital-analog conversion; Logic arrays; Mirrors; Parasitic capacitance; Signal resolution;
Conference_Titel :
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4244-1359-1
Electronic_ISBN :
978-1-4244-1360-7
DOI :
10.1109/ASSCC.2007.4425704