An 18-mW two-stage CMOS transimpedance amplifier for 10 Gb/s optical application

Author

Wang, Chao-Yung ; Wang, Chao-Shiun ; Wang, Chorng-Kuang

Author_Institution

Nat. Taiwan Univ., Taipei

fYear

2007

fDate

12-14 Nov. 2007

Firstpage

412

Lastpage

415

Abstract

This paper presents a low power and wideband transimpedancc amplifier (TIA) design for 10 Gb/s optical receiver. Using a 0.18-mum CMOS technology, this TIA adopts a two-stage topology with inductive shunt-peaking and series-peaking techniques to optimize the power consumption and bandwidth performance. The measured -3-dB bandwidth is 8.6 GHz in the presence of a 0.15-pF photodiode capacitance. The transimpedance gain is 59 dB Omega with only 18 mW power consumption from a 1.8-V supply. The measured input referred noise current is less than 25 pA / V Hz up to 9 GHz.

Keywords

amplifiers; integrated circuit design; low-power electronics; optical receivers; CMOS transimpedance amplifier; inductive shunt-peaking; optical application; optical receiver; series-peaking techniques; Bandwidth; Broadband amplifiers; CMOS technology; Energy consumption; Optical amplifiers; Optical design; Optical receivers; Semiconductor optical amplifiers; Stimulated emission; Topology; 10 Gb/s optical receiver; Inductive peaking; low power; series-peaking; shunt-peaking; transimpedance amplifier (TIA); wideband amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian

Conference_Location

Jeju

Print_ISBN

978-1-4244-1359-1

Electronic_ISBN

978-1-4244-1360-7

Type

conf

DOI

10.1109/ASSCC.2007.4425718

Filename

4425718