• DocumentCode
    2707629
  • Title

    Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment

  • Author

    Kotani, K. ; Shibata, T. ; Imai, M. ; Ohmi, T.

  • Author_Institution
    Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan
  • fYear
    1995
  • fDate
    15-17 Feb. 1995
  • Firstpage
    320
  • Lastpage
    321
  • Abstract
    Using a multiple-input high-functionality transistor neuron MOSFET (/spl nu/MOS), demonstrates a dramatic simplification of logic circuit configuration compared to conventional CMOS circuitry. The purpose of this paper is to present a new clocked /spl nu/MOS logic circuit scheme in which a clock-driven switching transistor attached to the floating gate is used not only to initialize the floating-gate charge but also to perform auto-adjusting of its inverting threshold that cancels the fluctuations arising from fabrication.
  • Keywords
    MOS logic circuits; /spl nu/MOS; auto-threshold-adjustment; clock-driven switching transistor; clocked-neuron-MOS logic circuits; fabrication fluctuations; floating gate; low power circuits; CMOS logic circuits; Circuit testing; Clocks; Logic circuits; MOSFETs; Nonvolatile memory; Pulse inverters; Sea measurements; Switching circuits; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-2495-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.1995.535583
  • Filename
    535583