DocumentCode
2707744
Title
A low power wide tange duty cycle corrector based on pulse shrinking/stretching mechanism
Author
Chen, Poki ; Chen, Shi-Wei ; Lai, Juan-Shan
Author_Institution
Nat. Taiwan Univ. of Sci. & Technol. Taipei, Taipei
fYear
2007
fDate
12-14 Nov. 2007
Firstpage
460
Lastpage
463
Abstract
A duty cycle corrector based on pulse shrinking/ stretching mechanism is presented. The proposed DCC has been rubricated in a TSMC 0.35mum standard CMOS process. An input duty cycle range of 30%~70% is achieved. The duty cycle error is within plusmn1.0% for the widest frequency operation range of 3MHz~60MHz ever fulfilled which makes the circuit best suited for ultra wide band applications. The chip area is merely 0.3 x 0.2 mm2 and the power consumption is 1. 1mW at 550 MHz.
Keywords
CMOS integrated circuits; clocks; low-power electronics; pulse width modulation; CMOS process; TSMC; duty cycle corrector; frequency 3 MHz to 660 MHz; power 1.1 mW; pulse shrinking mechanism; pulse stretching mechanism; size 0.35 mum; ultra wide band applications; Clocks; Delay lines; Frequency; Low pass filters; Propagation delay; Pulse amplifiers; Pulse circuits; Space vector pulse width modulation; Virtual manufacturing; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location
Jeju
Print_ISBN
978-1-4244-1359-1
Electronic_ISBN
978-1-4244-1360-7
Type
conf
DOI
10.1109/ASSCC.2007.4425730
Filename
4425730
Link To Document