Title :
A study of wafer level ESD testing
Author :
Yokoi, Kenichi ; Watanabe, Takeshi
Author_Institution :
Quality Manage. Div., NEC Corp., Kanagawa, Japan
Abstract :
This paper describes the possibility of performing the human body model (HBM) and machine model (MM) tests on a wafer. HBM capability when performed on a wafer is almost identical to that of a package; however, MM capability performed on a wafer is almost double that of a package due to the degradation of ESD pulses by parasitics in the equipment.
Keywords :
electrostatic discharge; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; test equipment; ESD pulse degradation; ESD pulses; HBM capability; HBM test; MM capability; MM test; human body model test; machine model test; package; test equipment parasitics; wafer level ESD testing; Circuit testing; Degradation; Electrostatic discharge; Fixtures; National electric code; Packaging machines; Performance evaluation; Semiconductor device modeling; Very large scale integration; Wafer scale integration;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
1-58537-018-5
DOI :
10.1109/EOSESD.2000.890021
