Study and Simulation of Power Amplifier Behavioral Model with Sparse Delay Taps

This paper analyzes the memory polynomial behavioral model with sparse delay taps, utilizing input and output data extracted from freescale semiconductor transistor MRF21030 model and designed circuit in ADS circumstance, simulate the memory polynomial model with sparse delay taps and compute normalized root mean square error (NRMS) and root mean square error (RMSE). Simulation results show that the proposed model has lower modeling error, better modeling performance, and output waveform of the model can be more close to real waveform. Put the memory model with sparse delay taps into the created adaptive digital baseband predistortion system and system-level simulation, simulation results demonstrate which performance can be more close to real system. So, this has a significant sense for designing real system.