• DocumentCode
    2707933
  • Title

    A 1.5dB NF, 5.8GHz CMOS low-noise amplifier with on-chip matching

  • Author

    Duster, J.S. ; Taylor, S.S. ; Zhan, J. H C

  • Author_Institution
    Intel Corp., Hillsboro
  • fYear
    2007
  • fDate
    12-14 Nov. 2007
  • Firstpage
    99
  • Lastpage
    102
  • Abstract
    In this paper we describe the design of an integrated 5.8 GIU low noise amplifier in 90 nm CMOS technology. The design is a tuned cascode LNA with on-chip matching that has a sufficiently low noise figure and high gain to enable high receiver sensitivity. The measured performance is NF=l.SdB, gain=28 dB, IIP3= -5 dBm and Pd=15mV; and NfW.SdB, gain=23 dB, HP3=-17 dBm and Pd=8 mV.
  • Keywords
    CMOS analogue integrated circuits; MMIC amplifiers; low noise amplifiers; CMOS low-noise amplifier; frequency 5.8 GHz; noise figure 1.5 dB; on-chip matching; receiver sensitivity; size 90 nm; CMOS technology; Current density; Impedance matching; Inductors; Linearity; Low-noise amplifiers; Noise figure; Noise measurement; Q factor; Radio frequency;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
  • Conference_Location
    Jeju
  • Print_ISBN
    978-1-4244-1359-1
  • Electronic_ISBN
    978-1-4244-1360-7
  • Type

    conf

  • DOI
    10.1109/ASSCC.2007.4425741
  • Filename
    4425741
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2707933