Title :
Planarization for 0.5 μm CMOS/BiCMOS technology
Author_Institution :
Cypress Semicond., San Jose, CA, USA
Abstract :
An all-SOG (spin-on glass) planarization process is proposed for 0.5-μm VLSI technology. The limited depth-of-focus of advanced lithography demands good planarization for both under-metal and inter-metal dielectric layers. A silicate SOG-based process was characterized for interpoly and poly-to-metal planarization, and a siloxane SOG-based process was characterized for inter-metal planarization. The poisoned via problem was solved by using a selective CVD W process for via filling. The specific via resistance is lower than 2×10-8 Ω-cm2 with a good yield (no failure for 240000 vias)
Keywords :
BIMOS integrated circuits; CMOS integrated circuits; VLSI; integrated circuit technology; metallisation; 0.5 micron; BiCMOS technology; CMOS technology; VLSI technology; W via filling; inter-metal dielectric layers; inter-metal planarization; multilevel interconnection; poisoned via problem; poly-to-metal planarization; selective CVD W process; silicate SOG-based process; siloxane SOG-based process; specific via resistance; spin on glass polarization process; via filling; yield; Annealing; BiCMOS integrated circuits; CMOS technology; Coatings; Furnaces; Planarization; Space technology; Temperature sensors; Time measurement; Wet etching;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE
Conference_Location :
Santa Clara, CA
DOI :
10.1109/VMIC.1990.127927
