DocumentCode
2708153
Title
A mixed parallel neural networks computing unit implemented in FPGA
Author
Xiaobin, Ma ; Lianwen, Jin ; Dongsheng, Shen ; Junxun, En
Author_Institution
Coll. of Electron. & Inf., South China Univ. of Technol., Guangzhou, China
Volume
1
fYear
2003
fDate
14-17 Dec. 2003
Firstpage
324
Abstract
A FPGA implementation architecture of neural network (NN) computing unit is proposed in this paper. In the computing unit, link parallelism is designed between the input layer and middle layer of NN; neuron parallelism is designed between the middle layer and output layer. Moreover, the method of hardware implementation of the sigmoid function of NN is improved and a new method for weight locating in computing unit is proposed, which can simply the implementation of the NN greatly.
Keywords
field programmable gate arrays; neural nets; FPGA; link parallelism; middle layer; mixed parallel neural networks computing unit; neuron parallelism; output layer; sigmoid function; Computer networks; Concurrent computing; Field programmable gate arrays; Hardware; Intelligent networks; Logic; Neural networks; Neurons; Parallel processing; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks and Signal Processing, 2003. Proceedings of the 2003 International Conference on
Conference_Location
Nanjing
Print_ISBN
0-7803-7702-8
Type
conf
DOI
10.1109/ICNNSP.2003.1279275
Filename
1279275
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