Title :
1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications
Author :
Hung, Yu-Cherng ; Tsai, Chung-Yang ; Liu, Bin-Da
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-/spl mu/m CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 /spl mu/s under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.
Keywords :
CMOS analogue integrated circuits; neural chips; neural nets; programmable circuits; 1 V; 1-V analog CMOS winner-take-all circuit; 5 mV; binary signals; k-loser-take-all capabilities; neurocomputing applications; post-layout simulation; programmable k-winner-take-all; response time; two-side searching capability; CMOS analog integrated circuits; CMOS technology; Circuit simulation; Delay; Dynamic range; Input variables; Rail to rail inputs; Signal resolution; Very large scale integration; Voltage;
Conference_Titel :
Neural Networks and Signal Processing, 2003. Proceedings of the 2003 International Conference on
Conference_Location :
Nanjing
Print_ISBN :
0-7803-7702-8
DOI :
10.1109/ICNNSP.2003.1279278
