Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 /spl mu/m CMOS process

ESD protection for RF applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfil these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 /spl mu/m CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme. The optimization of the diodes is then a key point which is detailed. A trade-off must be found between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as STI bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice.