Feasibility of a novel modular approach for planarization of a submicron triple-level metal CMOS process

The feasibility of a triple-level-metal submicron CMOS process using proven and manufacturable modules is demonstrated. While resist etchback and a silicate SOG (spin-on glass) sandwich are used for planarization at the polysilicon and first metal, respectively, neither of these process modules is feasible for the second-metal planarization due to the severe aspect ratios at this stage of the process. With resist etchback, voiding occurred in the deposited PECVD (plasma-enhanced chemical vapor deposition) layer prior to etchback, while with silicate SOG severe cracking was observed. Both these problems were resolved with a combined process where a thin SOG layer was used to prevent void formation in the subsequent PECVD layer, and the resist etchback scheme was then used to fully planarize prior to the third-metal deposition. Excellent planarity was obtained with <5% resistance differences measured on third metal running over and without topography. While reliability aspects have not yet been evaluated, it is not expected to be an issue based on previous experience with both silicate SOG and resist etchback planarization