Title :
Hot carrier degradation and ESD in submicron CMOS technologies: how do they interact?
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
In this paper, the phenomenon of channel hot carrier (CHC) induced degradation in transistors and its relation to ESD reliability is reviewed. The principles of CHC and the trade-off with ESD during technology development from channel/drain engineering, including consideration for mixed voltage designs, are discussed. Also, latent damage due to ESD-induced effects on CHC are considered. Finally, it is shown how the generation of hot carriers can help in the optimization of the performance of advanced ESD protection concepts.
Keywords :
CMOS integrated circuits; MOSFET; circuit optimisation; electrostatic discharge; hot carriers; integrated circuit reliability; protection; CHC induced degradation; CMOS technology; ESD; ESD protection concepts; ESD reliability; ESD-induced effects; channel hot carrier induced degradation; channel/drain engineering; hot carrier degradation; hot carrier degradation/ESD interaction; hot carriers; latent damage; mixed voltage designs; optimization; technology development; CMOS technology; Charge carrier processes; Degradation; Electrons; Electrostatic discharge; Hot carriers; MOSFETs; Reliability engineering; Silicon; Voltage;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
1-58537-018-5
DOI :
10.1109/EOSESD.2000.890087
