Automated source code annotation for timing analysis of embedded software

Virtual platforms are widely applied for embedded software protoyping and analysis. We introduce here an automatic annotation and estimation technique for the dynamic time analysis of embedded software. The annotation technique automatically inserts marks into the software, which can later be identified at assembler code level in order to back-annotate them with timing or power information. Our graph based technique applies automated labeling of basic blocks to aid in efficient construction of basic blocks for the disassembler. The graph is compacted for efficiency and a novel graph traversal technique is applied to estimate the flow cost. The timing estimates are later back annotated to the source code with the help of identifiers which are then used in SystemC simulations. Our technique can be easily deployed across variety of architectures as it is compiler-independent and does not implement any architecture specific features to estimate the time. The option to back-annotate the timing estimates avoids the requirement to recompile the entire model to get the same information before simulation.