Title :
A 65nm Pure CMOS one-time programmable memory using a two-port antifuse cell implemented in a matrix structure
Author :
Matsufuji, Kensuke ; Namekawa, Toshimasa ; Nakano, Hiroaki ; Ito, Hiroshi ; Wada, Osamu ; Otsuka, Nobuaki
Author_Institution :
Toshiba Corp., Kawasaki
Abstract :
A pure CMOS one-time programmable (PCOP) memory using an antifuse is presented. PCOP memory adopts two-port cell architecture implemented in a matrix structure. This architecture achieves optimization of performance both for programming and reading. Furthermore, it solves the write disturb problem and realizes pseudo "1" read test. An 8 Kbit macro is developed utilizing a 65 nm pure CMOS logic technology. The cell area and the macro size are 15.3 mum2 and 0.244 mm2, respectively.
Keywords :
CMOS logic circuits; CMOS memory circuits; PROM; memory architecture; CMOS logic technology; PCOP memory; matrix structure; pure CMOS one-time programmable memory; size 65 nm; storage capacity 8 Kbit; two-port antifuse cell; write disturb problem; Breakdown voltage; CMOS logic circuits; CMOS memory circuits; CMOS technology; Logic programming; MOSFETs; Parasitic capacitance; Redundancy; Temperature distribution; Testing;
Conference_Titel :
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4244-1359-1
Electronic_ISBN :
978-1-4244-1360-7
DOI :
10.1109/ASSCC.2007.4425768
