A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme

We propose an MRAM macro architecture for SoCs to reduce their area size. The .shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology´, which enables the same fast access time as and with smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-mum CMOS process and a 0.24-mum MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64 hits of data. Area size is reduced by more than 30%. By introducing a leakage-replication (LR) read scheme, 50-ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.