Title :
A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS
Author :
Kuramochi, Yasuhide ; Matsuzawa, Akira ; Kawabata, Masayuki
Author_Institution :
Advantest Lab. Ltd., Sendai
Abstract :
We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital blocks has been fabricated in a 0.18-mum CMOS process and consumes 110muW at 1.8 V power supply. With the calibration it achieves 9.0-dB improvement of SNDR and 23.3dB improvement of SFDR. The measured SNDR and SFDR are 51.1 dB and 69.8 dB respectively.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; comparators (circuits); digital-analogue conversion; low-power electronics; CMOS; capacitor; charge redistribution digital-to-analog converter; comparator; gain 23.3 dB; gain 51.1 dB; gain 69.8 dB; gain 9 dB; linearity calibration; power 110 muW; size 0.18 mum; successive approximation analog-to-digital converter core; voltage 1.8 V; word length 10 bit; Analog-digital conversion; CMOS process; Calibration; Capacitors; Digital-analog conversion; Linearity; Power supplies;
Conference_Titel :
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4244-1359-1
Electronic_ISBN :
978-1-4244-1360-7
DOI :
10.1109/ASSCC.2007.4425771
