Title :
A novel NMOS transistor for high performance ESD protection devices in 0.18 /spl mu/m CMOS technology utilizing salicide process
Author :
Kim, Chang-Su ; Park, Hong-Bae ; Bung-Gwan Kim ; Kang, Dae-Gwan ; Myoung-Goo Lee ; Si-Woo Lee ; Jeon, Chan-Hee ; Wan-Gu Kim ; Yoo, Young-Jae ; Yoon, Han-Sub
Author_Institution :
Memory R&D Div., Hyundai Electron. Ind. Co. Ltd., Kyunggi, South Korea
Abstract :
The electrostatic discharge (ESD) threshold of fully salicided grounded-gate NMOS transistors (ggNMOSTs) and partially salicided ggNMOSTs consisting of dummy-gate and N-well resistor was studied by transmission line pulse (TLP) I-V curves, and HBM and machine model (MM) robustness. The state-of-the-art 0.18 /spl mu/m cobalt salicide CMOS process is used, and the thickness of the gate dielectric material is 35 /spl Aring/. Fully salicided ggNMOSTs have much lower values of second breakdown current (It2) than partially salicided ggNMOSTs, and with multi-finger structures, only partially salicided ggNMOSTs turn on uniformly. Using these partially salicided NMOSTs as protection devices, we acquired ESD immunity of >2 kV (HBM) and >200 V (MM).
Keywords :
CMOS integrated circuits; MOSFET; cobalt compounds; dielectric thin films; electrostatic discharge; integrated circuit metallisation; integrated circuit reliability; protection; semiconductor device breakdown; semiconductor device metallisation; 0.18 micron; 2 kV; 200 V; 35 angstrom; CMOS technology; CoSi/sub 2/-SiO/sub 2/-Si; ESD immunity; ESD protection devices; ESD threshold; HBM; HBM robustness; MM robustness; N-well resistor; NMOS transistor; TLP I-V curves; cobalt salicide CMOS process; dummy-gate; electrostatic discharge; fully salicided ggNMOSTs; fully salicided grounded-gate NMOS transistors; gate dielectric material thickness; ggNMOSTs; machine model; multi-finger structures; partially salicided ggNMOSTs; protection devices; salicide process; second breakdown current; transmission line pulse I-V curves; uniform ggNMOST turn-on; CMOS process; Cobalt; Dielectric materials; Electrostatic discharge; MOSFETs; Protection; Resistors; Robustness; Semiconductor device modeling; Transmission lines;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
1-58537-018-5
DOI :
10.1109/EOSESD.2000.890109