DocumentCode :
2708672
Title :
Penryn: 45-nm next generation Intel® core™ 2 processor
Author :
George, Varghese ; Jahagirdar, Sanjeev ; Tong, Chao ; Smits, Ken ; Damaraju, Satish ; Siers, Scott ; Naydenov, Ves ; Khondker, Tanveer ; Sarkar, Sanjib ; Singh, Puneet
Author_Institution :
Intel Corporation Folsom, Santa Clara, CA, USA
fYear :
2007
fDate :
12-14 Nov. 2007
Firstpage :
14
Lastpage :
17
Abstract :
This paper describes Penryn (codename), Intel–s next generation family of processors implemented in a 45nm High-k metal gate silicon process technology and designed to meet a wide range of power envelopes and market segments. It is a dual-core, 64-bit CPU based on the Core™ microarchitecture with a unified 24-way L2 cache of 6MB. Key new features in Penryn include a Fast Radix- 16 Divider, an SSE4 instruction set, a radically new Power Management state (Deep Power Down) and Enhanced Dynamic Acceleration Technology (EDAT). Active and leakage power reduction techniques are used throughout the design to reduce power consumption while not compromising the scalability requirements. The chip is offered in various package technologies including a MCP version for the Quad-core products.
Keywords :
Acceleration; Energy consumption; Energy management; High K dielectric materials; High-K gate dielectrics; Microarchitecture; Process design; Scalability; Silicon; Technology management;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location :
Jeju City, South Korea
Print_ISBN :
978-1-4244-1359-1
Electronic_ISBN :
978-1-4244-1360-7
Type :
conf
DOI :
10.1109/ASSCC.2007.4425784
Filename :
4425784
Link To Document :
بازگشت