Title :
Chip-level simulation for CDM failures in multi-power ICs
Author :
Lee, Jaesik ; Huh, Yoonjong ; Chen, Jau-Wen ; Bendix, Peter ; Kang, Sung-Mo
Author_Institution :
Illinois Univ., Urbana, IL, USA
Abstract :
This paper presents a new chip-level simulation methodology for charged-device model (CDM) failure analysis in multi-power ICs. A circuit model considering reported CDM failures and efficient simulation is proposed and incorporated with the circuit-level ESD simulator, iETSIM. The CDM behaviors in multi-power ICs are analyzed and the vulnerable sites to CDM stress can be predicted by chip-level simulation. Simulation results are verified by CDM testing of a 0.25 /spl mu/m CMOS ASIC and show good correlation. This simulation methodology at the full-chip level enables us to address CDM failure issues before the detailed chip floorplan and power grid networking are started.
Keywords :
CMOS integrated circuits; application specific integrated circuits; circuit simulation; electrostatic discharge; failure analysis; integrated circuit layout; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; 0.25 micron; CDM behavior; CDM failure; CDM failure analysis; CDM failures; CDM stress; CDM testing; CMOS ASIC; charged-device model failure analysis; chip floorplan; chip-level simulation; chip-level simulation methodology; circuit model; full-chip level; iETSIM circuit-level ESD simulator; multi-power ICs; power grid networking; simulation; simulation methodology; Analytical models; Application specific integrated circuits; Circuit simulation; Circuit testing; Electrostatic discharge; Failure analysis; Power grids; Predictive models; Semiconductor device modeling; Stress;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
1-58537-018-5
DOI :
10.1109/EOSESD.2000.890116
