• DocumentCode
    2708729
  • Title

    A PCI-express Gen2 transceiver with adaptive 2-Tap DFE for up to 12-meter external cabling

  • Author

    Yeh, Tse-Hsien ; Wang, Wei-Yu ; Wang, Wen-Liang ; Lin, Yu-Hong ; Cheng, Ying-Lien ; Chou, Tsung-Hsin ; Lin, Jyhfong

  • Author_Institution
    VIA Technol. Inc., Taipei
  • fYear
    2007
  • fDate
    12-14 Nov. 2007
  • Firstpage
    30
  • Lastpage
    33
  • Abstract
    The most updated specification of PCI-Express External Cabling 1.0 only specifies Gen1 (2.5 Gbps) for short-reach usage. This proposed transceiver architecture not only increases the link rate from Genl to Gen2 (5 Gbps), but also extends link range from short-reach to long-reach using a 12-meter 26AWG cable. The S21 of such a cable is -20 dB at 2.5 GHz. The new receiver achieves jitter tolerance at the far-end terminal followed by such a cable is 0.76UI, with a random jitter of 0.31 UI, under the BER of 10-12. This design has been fabricated in TSMC 80 nm CMOS process, with the die area of 0.4 mm2 for each lane.
  • Keywords
    CMOS integrated circuits; decision feedback equalisers; peripheral interfaces; telecommunication cables; transceivers; CMOS process; External Cabling; PCI-express Gen2 transceiver; adaptive 2-Tap DFE; distance 0 m to 12 m; external cabling; frequency 2.5 GHz; Bandwidth; Circuits; Clocks; Decision feedback equalizers; Detectors; Jitter; Multiplexing; Phase locked loops; Switches; Transceivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
  • Conference_Location
    Jeju
  • Print_ISBN
    978-1-4244-1359-1
  • Electronic_ISBN
    978-1-4244-1360-7
  • Type

    conf

  • DOI
    10.1109/ASSCC.2007.4425788
  • Filename
    4425788