DocumentCode
2708776
Title
Analog design challenges in nanometer CMOS technologies
Author
Sansen, Willy
Author_Institution
KULeuven, Leuven
fYear
2007
fDate
12-14 Nov. 2007
Firstpage
5
Lastpage
9
Abstract
This paper provides a review of all important effects in nm CMOS technologies, with 1 volt supply voltages. They are the reduction of the transconduction, the increase of the gate current, the noise and the mismatch. It is followed by an overview of amplifiers/filters configurations with both Gate and Bulk drives. A large number of sub-1 volt circuits are then provided for sake of illustration, including sigma-delta modulators.
Keywords
CMOS analogue integrated circuits; filters; integrated circuit design; nanoelectronics; operational amplifiers; sigma-delta modulation; amplifiers-filters configurations; analog design challenges; gate current; nanometer CMOS technologies; sigma-delta modulators; transconduction reduction; voltage 1 V; Analog circuits; Boosting; CMOS analog integrated circuits; CMOS technology; Circuit noise; Filters; Noise cancellation; Operational amplifiers; Threshold voltage; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location
Jeju
Print_ISBN
978-1-4244-1359-1
Electronic_ISBN
978-1-4244-1360-7
Type
conf
DOI
10.1109/ASSCC.2007.4425792
Filename
4425792
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