Title :
Design-for-secure-test for crypto cores
Author :
Shi, Youhua ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo
Author_Institution :
Waseda Univ., Tokyo, Japan
Abstract :
Scan technology carries the potential of being misused as a ¿side channel¿ to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.
Keywords :
VLSI; automatic testing; boundary scan testing; cryptography; design for testability; flip-flops; integrated circuit testing; crypto cores; design-for-secure-test; secret information; side channel; stimuli launched flip flop; Computer hacking; Design automation; Elliptic curve cryptography; Flip-flops; Hardware; Information security; Testing; Timing; Tin; Very large scale integration;
Conference_Titel :
Test Conference, 2009. ITC 2009. International
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4868-5
Electronic_ISBN :
978-1-4244-4867-8
DOI :
10.1109/TEST.2009.5355900
