• DocumentCode
    2709168
  • Title

    A polysilicon hard-mask/spacer process for sub-0.5 micron ULSI contacts

  • Author

    Sun, S.W. ; Woo, M.P. ; Kawasaki, H.

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • fYear
    1990
  • fDate
    12-13 Jun 1990
  • Firstpage
    474
  • Lastpage
    476
  • Abstract
    A contact formation process for fabricating sub-0.5-μm contacts is proposed. By using a thin polysilicon layer and a spacer as the hard mask, the contact process bias can be reduced by as much as 0.4-0.5 μm. The feasibility of this contact technology for ULSI applications is demonstrated by low contact resistivity (<5×10-8 Ω-cm2) and well-behaved sub-0.5-μm MOSFET devices
  • Keywords
    MOS integrated circuits; VLSI; insulated gate field effect transistors; integrated circuit technology; metallisation; ohmic contacts; MOSFET devices; ULSI contacts; contact formation process; contact process bias; contact technology; feasibility; hard mask; low contact resistivity; polycrystalline Si; polysilicon hard-mask/spacer process; sub-0.5-μm contacts; thin polysilicon layer; CMOS technology; Conductivity; Contact resistance; Etching; Integrated circuit technology; Lithography; Resists; Space technology; Titanium; Ultra large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE
  • Conference_Location
    Santa Clara, CA
  • Type

    conf

  • DOI
    10.1109/VMIC.1990.127934
  • Filename
    127934
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2709168