Fractional-N Direct Digital Frequency Synthesis with a 1-Bit Output

Author

Rode, Jeremy ; Swaminathan, Ashok ; Galton, Ian ; Asbeck, Peter M.

Author_Institution

California Univ., San Diego, CA

fYear

2006

fDate

11-16 June 2006

Firstpage

415

Lastpage

418

Abstract

A novel digital frequency synthesis (DDS) architecture with a 1-bit output is proposed, simulated, and demonstrated. A new noise shaping quantization algorithm is also evaluated and used within the proposed DDS system. Large tuning ranges and rapid (open loop) response characteristics are achieved with only a static reference frequency input, without the use of analog components, allowing easy integration in digital CMOS processes. Across a tuning range of 10% f_ref, a noise floor of -80 dBc/Hz and spurious tones lower than -50 dBc are possible with this system

Keywords

CMOS digital integrated circuits; circuit tuning; direct digital synthesis; integrated circuit noise; DDS architecture; digital CMOS process; digital frequency synthesis architecture; fractional-N direct digital frequency synthesis; noise shaping quantization algorithm; static reference frequency input; Circuit optimization; Clocks; Counting circuits; Feedback loop; Frequency conversion; Frequency synthesizers; Integrated circuit synthesis; Quantization; Signal synthesis; Tuning; CMOS digital integrated circuits; Frequency synthesizers; Quantization; Sigma-delta modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2006. IEEE MTT-S International

Conference_Location

San Francisco, CA

ISSN

0149-645X

Print_ISBN

0-7803-9541-7

Electronic_ISBN

0149-645X

Type

conf

DOI

10.1109/MWSYM.2006.249559

Filename

4014919