Finely tunable standard cells for high-speed ASMIC

Author

Takayanagi, T. ; Sakurai, T. ; Sawada, K. ; Nogami, K. ; Iizuka, T.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1989

fDate

17-19 May 1989

Firstpage

134

Lastpage

138

Abstract

A finely tunable standard cell (FTSC) method is introduced to cope with the complexity and high-speed nature of application-specific memory ICs (ASMICs). The method is applied to an integrated cache memory, a typical high-speed ASMIC, and achieves address-to-hit delay of 18 ns, which is comparable to that of a standard full-custom static RAM (SRAM). The FTSC offers the sizing capability of MOSFETs and stable delay elements composed of poly-Si resistors

Keywords

application specific integrated circuits; buffer storage; cellular arrays; integrated memory circuits; 18 ns; address-to-hit delay; application-specific memory ICs; finely tunable standard cell; high-speed ASMIC; integrated cache memory; polysilicon resistors; sizing capability; stable delay elements; Cache memory; Delay; Design methodology; Logic functions; Logic gates; MOSFETs; Parasitic capacitance; Pins; Timing; Tunable circuits and devices;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Conference_Location

Taipei

Type

conf

DOI

10.1109/VTSA.1989.68599

Filename

68599

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2710485